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Simulation of cryptographic algorithms using FPGA
Németh, František ; Mašek, Jan (referee) ; Smékal, David (advisor)
Bachelor thesis is dealing with a cipher standard AES and with a design of encryption and decryption components for AES in special modes of operation. Programming language is VHDL. In theoretical part of thesis is a further descriptions of AES and behaviour of block cipher operation modes. Furthermore the brief description of VHDL, FPGA and NetCOPE framework is a piece of theoretical part as well. The practical part contains designs which are made in developing environment Vivado from Xilinx. Programmed modes of operation are ECB, CBC, CTR and CFB. Simulation outputs and synthesis results are summerized in tables.
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Methods for quadrature modulator imbalance compensation
Povalač, Karel ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
Quadrature modulator (demodulator) is used in transmitting (receiving) part of many devices. Unwanted imbalance can influence amplitude, phase or DC offset of modulator (demodulator). Correction of imbalance was a main subject of thesis. Simulations of these methods were created in MATLAB and results were compared. Basics of methods were implement on programmable logic field by program Xilinx ISE. Development kit V2MB1000 with analogue board Memec P160 was chosen for this purpose. In the last part were compare simulation results with practical measurement.
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FPGA core for data displaying on computer monitor using VGA port
Pišl, Adam ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
The aim of this project is to perform the study of a driver for controlling computer monitor using VGA port. The driver is based on FPGA which is used to generate VGA signals. The main purpose of the project is to design a hardware core for gate array which can be used as part of some complex FPGA design to provide a comfortable user interface. The project describes the main part of the VGA driver – module for generating control signals and module for displaying text information that is sent from a PC via serial port interface.
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Development Board for 32-bit Microcontroller Atmel AT91SAM9261
Demín, Martin ; Slaný, Karel (referee) ; Šimek, Václav (advisor)
Vestavený hardware je velice populární v této době. Proto jsme se rozhodli vytvořit desku s mikrokontrolérem AT91SAM9261 spolu so standartným a nestandartným hardwarem. Standartným, běžným by se dal nazvat port LAN alebo audio vstup-výstup. Nestandartným, špecialním by mohl být obvod FPGA firmy Xilinx o velikosti 200k. Toto dovoluje využít zažízení v oblastech, kde výpočetní síla obyčejnýho CPU již není dostačující.
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Microprocessor system IP core generator
Kerber, Rostislav ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
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Sample assignments in VHDL
Huzlík, Petr ; Macho, Tomáš (referee) ; Holek, Radovan (advisor)
This bachelor’s study connects on semestral project and is focused on VHDL language and FPGA and CPLD circuits by Xilinx. The aim of this study is to describe how to work with profossional design tool WebPack. Documents detaily describes how to create new project on advanced level - with emphasis on methodiology and examples from practice in VHDL lenguage.
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Digital predistorters for amplifier linearization
Kroužil, Miroslav ; Valenta, Václav (referee) ; Maršálek, Roman (advisor)
In this work I describe digital predistortion in baseband used for amplifier linearization. Non-linearity is one of the worst disadvantages of Power amplifiers and decreasing of its is useful from many reasons. Work examines system which contains: Data source, which is represented by QPSK or OFDM modulator, predistorter, Power amplifier (model of non-linearity) and unit used to update coeficients for predistorter adaptation. System is simulated in MATLAB and Xilinx (simulation by ModelSim). Results are compared, described and commented.
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Logic analyzer module based on PCIe card
Juřík, Tomáš ; Macho, Tomáš (referee) ; Valach, Soběslav (advisor)
The goal of this bachelor's thesis is to implement simple FPGA-based logic analyzer connected to PCI-Express bus. Furthermore four counters are implemented to generate testing dataset. This thesis describes a fundamental priciple and use of logic analyzer. An overview of Spartan-3 PCI Express Starter Kit development board and Xilinx Spartan-3 field-programmable gate array anrchitecture is given. Stages of logic analyzer development are detailed as well.
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Mixed criticalities in motor control applications on Zynq platform
Pamánek, David ; Veselý, Libor (referee) ; Blaha, Petr (advisor)
This thesis contains introduction to PMS motor control using development board ZedBoard with Xilinx Zynq-7000 SoC. After that, there is a description of development environment Vivado and other modules. Finally, it contains description or created modules in Vivado environment which were combined together with peripheral drivers to demonstrate field oriented motor control algorithm of small PMS motor.
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Autonegotiation implementation for 25 - 100 Gbps Ethernet interfaces
Válek, Vladislav ; Jedlička, Petr (referee) ; Tomašov, Adrián (advisor)
This bachelor's thesis addresses the design of the auto-negotiation component for network interface cards controlled by FPGAs. Auto-negotiation function allows to advertise the available communication parameters, like the link speed, the transmission pause ability or Forward Error Correction (FEC) ability, by either side of the common link and determine the common abilities, which will be used to establish a connection. In the beginning, the internal parts of Xilinx UltraScale+ FPGA family are introduced with greater emphasis on the description of GTY transceivers. In the next chapter are introduced the mechanisms of auto-negotiation function as described in clause 73 of the IEEE 802.3-2018 standard. The design here is created for Ethernet interfaces running at speed 25~Gbps and is written in VHDL language. The next chapter describes the necessary steps which are required for the implementation on the FPGAs, where high-speed transceivers are in use. Function of the created design was then checked within a simulation and the correspondent results are also provided in this thesis. In the end, the testing of the designed auto-negotiation component took place for which the network card with Vitex 7 UltraScale+ FPGA was used. The testing process includes the use of the Integrated Logic Analyzer (ILA) which was inserted into final design. The achieved results from testing of both, the auto-negotiation process and surrounding physical layer processes, are described here with proper commentary.
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